816 BEAT

CMD has recently released the next generation of SuperCPU accelerators, the SuperCPU v2. In addition to providing a Commodore 128 option, the version 2 hardware and firmware also replace the older SuperCPU 64, providing enhancements and features that apply to both SuperCPU models. In this installment of 816 Beat, we'll not only look at new additions in v2, but also point out some things that have changed.
 
 

SuperCPU 128

Of course, the big news is that the SuperCPU 128-the only accelerator ever created for the Commodore 128's native mode-is now a reality. The new SuperCPU v2 hardware sports 256K of Static RAM (SRAM) on its main board, allowing it to emulate all the RAM and ROM of both the Commodore 64 and 128. 

As with the original SuperCPU 64, two of the 64K banks of RAM (128K) are mapped into the 65816's Bank 0 and 1. However, the additional 128K added to provide Commodore 128 compatibility is not mapped in this manner, and is instead switched into Banks 0 and 1 in place of the original 128K as necessary. Under this scheme, the 65816's Bank 0 always contains computer RAM in any mode; in 128 mode, this will be either the 128's Ba nk 0 or Bank 1 RAM, depending on which is active. The 65816's Bank 1 RAM will contain ROM data; by default the ROM data present will always be the C-64 ROM except when given C-128 ROM segments are mapped in while using 128 mode. These ROM images are further mirrored into the 65816's Bank 0 RAM as necessary to make a composite image of the memory as it would exist on a C-64 or C-128 computer.

While the overall scheme may seem somewhat complex, it maintains the ability to modify ROM segments directly in the 65816's Bank 1, and provides for mapping in 65816 expansion RAM beginning at Bank 2. The latter serves to maintain a standard memory map for both the SuperCPU 64 and SuperCPU 128, regardless of vintage (v1 or v2).
 
 

More Optimization Capabilities

Those familiar with the original SuperCPU 64 (v1) no doubt know that it has four possible configurations for mirroring of memory. These configurations are known as the 'Optimization Modes'. In the v2 hardware this has grown to eight 'base' configurations, most of which offer one or two special flags that bring the total number of optimization configurations available to 11 in 64 mode, and 19 in 128 mode. The table, 'Important SuperCPU Memory Locations' provides further insight into the configurations available.

Despite the addition of many new Optimization Modes, the new v2 hardware maintains backward compatibility with all modes available in the original SuperCPU. Any changes made to the new Enhanced Optimization Register ($D0B3) are reflected into the old Optimization Mode Flags ($D0B4), and vice-versa. This means that programs written to use the older registers will still achieve the desired results under the new version.

In looking over the new Optimization Modes, you'll see the special flags, labelled B and Z. The B flag controls the C-128 RAM Bank, so is only useful in 128 Mode on a SuperCPU 128. The Z flag controls mirroring of Zero Page and Stack ($0000-$01FF). Turning off mirroring of these latter areas vastly increases the performance of programs since many of the microprocessor's instructions use these areas of memory. This particular optimization has been included in the default setting of the SuperCPU v2, meaning that programs will generally run faster than ever without any modifications by the user.

Bear in mind that Optimization Modes only affect the true physical addresses specified by each; if you use the Commodore 128's ability to relocate Zero page to some other physical address, that area won't be optimized by the Z flag optimization.

In addition to having all the new Optimization Modes, the new v2 release has made accessing some of the more useful ones more easily available to users by setting up a key combination for switching between modes. From BASIC's direct command mode, using the CONTROL and BACK ARROW keys together will toggle through the available modes. (Note: Like many of the JiffyDOS key commands, this function doesn't work once a program is running or while in quote mode).
 
 

Other Registers

Another new register added in the v2 hardware is the SuperCPU Mode Detect Register ($D0B2). This register lets you determine if a detected SuperCPU is a v1 or v2, and if it is a v2 you can also find out whether it is in 64 or 128 mode.

There are no other additional registers, but there has been one other change to an existing one. In the register at location $D0B6, the bit that previously held the status of the reset switch (bit 6) is no longer valid in v2.
 
 

Timing Notes

Several timing changes have been made in the v2 hardware to improve performance. Probably the most beneficial is that color RAM is no longer treated as I/O, but instead as standard mirrored memory. This allows full speed reads of this area, and writes will also be at full speed, provided the cache isn't waiting for another operation to complete.

Access to the special RAM in the I/O area ($D200-$D3FF) now takes only 1 cycle (previously it required 1.5 cycles). The registers in the $D07x and $D0Bx ranges have also been optimized to work at full speed (any previous read or write to these registers caused the system to wait for the next 1 MHz cycle). Location $01 has also gotten a boost to full speed in 64 mode (previously writes waited for the next 1 MHz cycle, while reads have always been at 20 MHz.

The creation of a 128 mode in the SuperCPU 128 has brought about some additional special timing requirements. Reading or writing locations $01 or $FF00 in 128 mode causes the SuperCPU to wait for the next 1 MHz cycle. Reads from $D600, $D601 and $FF01-$FF04 also cause the SuperCPU to wait for the next 1 MHz cycle, though writes to these locations use the cache. Note that after any actual VDC chip access, further VDC access is blocked during the following 1 MHz cycle to allow the video chip enough time to complete the operation.
 
 

Important SuperCPU Memory Locations

Location                       Purpose
$D074(1)        (53364)        VIC Bank 2/GEOS Optimization (mirror $8000-$BFFF)
$D075(1)        (53365)        VIC Bank 1 Optimization (mirror $4000-$7FFF)
$D076(1)        (53366)        BASIC Optimization (mirror $0400-$07FF)
$D077(1)        (53367)        No Optimization (mirror all memory) (v1 default)
$D07A(2)        (53370)        Software Speed Select - Normal (1 MHz or 2 MHz in
                                128 Fast mode)
$D07B(3)        (53371)        Software Speed Select - Turbo (20 MHz) (*$D079)
$D07E(2)        (53374)        Hardware Register Enable
$D07F(2)        (53375)        Hardware Register Disable (*$D07D)
$D0B0(6)        (53424)        SuperCPU Mode Detect Register
                                 00xxxxxx = SuperCPU v2 in 128 mode
                                 01xxxxxx = SuperCPU v2 in 64 mode
                                 11xxxxxx = SuperCPU v1, no SuperCPU, or 
                                             SuperCPU disabled
$D0B2(4)        (53426)        Bit 7: Hardware Register Enable Flag (1=Enabled)
                               Bit 6: System 1 MHz Flag (1=Enabled)
$D0B3(5,7)      (53427)        Enhanced Optimization Register (v2 only)
                                 00xxx1BZ = VIC Bank 0, $0000-$3FFF
                                 01xxx0B0 = VIC Bank 1, $4000-$7FFF
                                 00xxx0B0 = VIC Bank 2/GEOS, $8000-$BFFF
                                 01xxx1B0 = VIC Bank 3, $C000-$FFFF
                                 10xxx0B0 = BASIC Opt., $0400-$07FF
                                 11xxx00Z = No Opt. All Mem., $0:0000-$1:FFFF 
                                             (v2 default)
                                 11xxx1BZ = No Opt. per Bank, $0000-$FFFF
                                 10xxx100 = Full Optimization (no mirroring of 
                                             any memory)
$D0B4(5)        (53428)        Bits 7 & 6: Optimization Mode Flags:
                                 00xxxxxx = VIC Bank 2/GEOS Optimization Enabled
                                 01xxxxxx = VIC Bank 1 Optimization Enabled
                                 10xxxxxx = BASIC Optimization Enabled
                                 11xxxxxx = No Optimization
$D0B5(6)        (53429)        Bit 7: JiffyDOS Switch Flag (1=Enabled)
                               Bit 6: Speed Switch Flag (1=Normal, 0=Turbo)
$D0B6(6)        (53430)        Bit 7: Processor Emulation Mode Flag 
                                       (1=Emulation)
                               Bit 6: Reset Switch Flag (1=Switch pressed) 
                                       (v1 only)
$D0B8(4)        (53432)        Bit 7: Software Speed Flag (1=Normal, 0=Turbo)
                               Bit 6: Master Speed Flag (1=Normal via any 
                                       source)
$D0BC(5)        (53436)        Bit 7: DOS Extension Mode Flag (1=Enabled)
                               Bit 6: RAMLink Hardware Registers Flag 
                                       (1=Enabled)
$D200-$D2FF(4)  (53760-54015)  System RAM 
$D300-$D3FF(5)  (54016-54271)  User RAM (available for user programs) 

Notes:
(1) Write only, hardware registers must be enabled to activate location.
(2) Write only, active with hardware registers enabled or disabled.
(3) Write only, active with hardware registers enabled or disabled, but does 
    not over-ride hardware Speed switch.
(4) Read only with hardware registers disabled, Read/Write with hardware 
    registers enabled, write access reserved for system only.
(5) Read only with hardware registers disabled, Read/Write with hardware 
    registers enabled.
(6) Read only with hardware registers enabled or disabled (write with hardware 
    registers enabled has no effect).
(7) Changing values in this area affects all other optimization mode registers, 
    and changing other optimization mode registers affect this location. The B 
    flag assigns control of this register to a specific Commodore 128 Bank 
    (0=Bank 0, 1=Bank 1), while the Z flag contols mirroring of Zero Page and 
    Stack memory ($0000-$01FF) (0=mirroring on, 1=mirroring off). Default for 
    Z is 1, B is 0.
(*) Denotes a duplicate register location.

IMPORTANT NOTE: Enabling the SuperCPU hardware registers also causes
some changes in the Kernal ROM memory map ($E000-$FFFF). To avoid problems,
do not leave the hardware registers enabled any longer than necessary. Also
note that mirroring of I/O is always performed when I/O is mapped in.