SuperCPU Programming Info

Programming Information

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MEMORY DIFFERENCES

Due to the very nature of what the SuperCPU is and does, there are differences in portions of your computer's memory map when the SuperCPU is enabled. These differences fall into two main segments of memory: the I/O area, where the SuperCPU registers are located; and the Kernel, which has been patched out of necessity.

Within the I/O space, there are three specific ranges of memory that are affected: $D070-$D07F; $D0B0-D0BF; and $D200-$D3FF.

SUPERCPU REGISTERS

All registers are located in VIC register mirror locations. On a stock system, reading these locations always returns an $FF, and writing these locations does not fall through into RAM while I/O is switched in. Therefore, these locations are generally considered useless on a stock system when I/O is switched in.

The registers in the $D07x range and some of the flags in the $D0Bx range are write-sensitive switches. In other words, any write (POKE or machine language 'store' operation) to a register in that range will cause the register's assigned function to activate, regardless of the value being written into the location.

Also note that the new registers have been created using a 'sandwich' assignment that minimizes the chances of memory fill problems. In other words, a memory fill might trigger a slowdown when writing to the register that provides this capability; however, the very next location written to in either direction causes a speed-up, so the SuperCPU could only be slowed down inadvertently for the duration of one machine instruction. The same situation applies to the hardware enable and disable registers: the locations on either side of the hardware enable register is a hardware disable register. Therefore, memory fills in either direction could only inadvertently enable the hardware for one machine instruction operation. Programmers are urged to use the documented locations (and not the 'duplicates') to maintain a 'standard location' for calling these functions.

Important SuperCPU Memory Locations

Location        Note   Purpose
$D074  (53364)  (1)     GEOS Optimization (mirror VIC Bank 02, $8000-$BFFF)
$D075  (53365)  (1)     VIC Bank 01 Optimization (mirror $4000-$7FFF)
$D076  (53366)  (1)     BASIC Optimization (mirror $0400-$07FF)
$D077  (53367)  (1)     No Optimization (default; mirror all memory)
$D07A  (53370)  (2)     Software Speed Select - Normal (1 MHz)
$D07B  (53371)  (3)     Software Speed Select - Turbo (20 MHz) (*$D079)
$D07E  (53374)  (2)     Hardware Register Enable
$D07F  (53375)  (2)     Hardware Register Disable (*$D07D)
$D0B2  (53426)  (4)     Bit 7: Hardware Register Enable Flag (1=Enabled)
                        Bit 6: System 1 MHz Flag (1=Enabled)
$D0B4  (53428)  (5)     Bits 7 & 6: Optimization Mode Flags:
                             00xxxxxx=GEOS Optimization Enabled
                             01xxxxxx=VIC Bank 01 Optimization Enabled
                             10xxxxxx=VIC Bank 02 Optimization Enabled
                             11xxxxxx=No Optimization
$D0B5  (53429)  (6)     Bit 7: JiffyDOS Switch Flag (1=Enabled)
                        Bit 6: Speed Switch Flag (1=1 MHz)
$D0B6  (53430)  (4)     Bit 7: Processor Emulation Mode Flag (1=Emulation)
                        Bit 6: Reset Switch Flag (1=Switch Pressed)
$D0B8  (53432)  (4)     Bit 7: Software 1 MHz Flag (1=1 MHz)
                        Bit 6: Master 1 MHz Flag (1=1 MHz via any source)
$D0BC  (53433)  (5)     Bit 7: DOS Extension Mode Flag (1=Enabled)
                        Bit 6: RAMLink Hardware Registers Flag (1=Enabled)
$D200-$D2FF (53760-54015) (4) RAM
$D300-$D3FF (54016-54271) (5) RAM (available for user programs)

Notes:: (1) Write only, hardware registers must be enabled to activate location.

IMPORTANT NOTE: Enabling the SuperCPU hardware registers also causes some changes in the Kernal ROM memory map ($E000-$FFFF). To avoid problems, do not leave the hardware registers enabled any longer than necessary.

RESERVED REGISTER LOCATIONS

In addition to the documented registers, there are undocumented locations in both the $D07x and $D0Bx ranges which are reserved for system use only. These locations are only active while the SuperCPU's hardware registers are enabled. Do not write to undocumented locations in these ranges while the hardware registers are enabled.

DETECTING A SUPERCPU

There are several possible methods to detect the presence of a SuperCPU on a computer. One of the more simple methods would be to check bit 7 of $D0BC. On a stock 64, this bit would always be high (logic 1), but on a SuperCPU it will normally be set to 0 whenever a user program is in control. The following BASIC program checks this bit and determines whether a SuperCPU is present and enabled:

100 X=ABS((PEEK(53433)AND128)=128)
110 IF X=0 THEN PRINT "SUPERCPU MODE"
120 IF X=1 THEN PRINT "STOCK MODE"
130 END

SOFTWARE SPEED CONTROL

When writing or modifying BASIC programs, you can easily control the speed using POKE commands. This might be desirable if you have a program with fixed timing loops, such as FOR/NEXT delays. To slow down a program, you would use POKE 53370,0. Likewise, to speed the program back up, use POKE 53371,0. Here's a brief programming example to clarify this further:

120 POKE 53370,0 : REM SLOW DOWN TO 1 MHZ
130 FOR I = 1 TO 1000 : REM FOR/NEXT TIMING LOOP
140 NEXT : REM FOR/NEXT TIMING LOOP
150 POKE 53371,0 : REM SPEED UP TO 20 MHZ

OPTIMIZING PROGRAMS

The optimization modes supply a means by which programmers, and in some cases users, can optimize their software to operate as quickly as possible. The advantage gained by optimization can be dramatic-a simple FOR/NEXT loop in BASIC executes more than twice as fast when the correct optimization mode is selected. Normally the SuperCPU needs to copy all of its own fast RAM contents into the slower RAM of the computer since it doesn't know where the VIC will be getting data from. If you know the VIC data requirements for a specific program, however, you can limit the amount of memory mirroring. To do so, you must enter three POKE commands: one to enable the hardware registers of the SuperCPU, a second to select the optimization mode, and a third to disable the hardware registers of the SuperCPU.

For example, to optimize a program that uses the standard text screen memory ($0400-$07FF) for the VIC, you would use the BASIC Optimization mode. To do this, load the program, but before running it enter:

POKE53374,0:POKE53366,0:POKE53375,0

and press RETURN. Similarly, you can use the same method to select any of the other optimization modes. To set the optimization for a program that uses VIC bank 01 ($4000-$7FFF) for screen or bit-mapped graphics, use:

POKE53374,0:POKE53365,0:POKE53375,0

To set the optimization for a program that uses VIC bank 02 ($8000-$BFFF) for screen or bit-mapped graphics, use:

POKE53374,0:POKE53364,0:POKE53375,0

To disable any of the optimization modes after a program has finished, either reset the SuperCPU, or use these POKE commands:

POKE53374,0:POKE53367,0:POKE53375,0

You can also use these pokes within your own programs, or programs that you are capable of modifying. Here's an example of a short BASIC program that turns on BASIC Optimization, prints to the screen, then disables optimization before ending:

10 POKE53374,0:POKE53366,0:POKE53375,0
20 PRINT CHR$(147);
30 FOR I = 1 TO 20 
40 : PRINT "HELLO"
50 NEXT
60 POKE53374,0:POKE53367,0:POKE53375,0
50 END

You can also use these methods in machine language programs, but instead of using POKE commands, use one of the store opcodes such as STA, STX or STY to perform the desired change. For example, the assembly code to enable BASIC Optimization might look like this:

STA $D07E ; ENABLE HARDWARE REGISTERS
STA $D076 ; SELECT BASIC OPTIMIZATION
STA $D07F ; DISABLE HARDWARE REGISTERS

Since the value stored doesn't matter, you needn't worry about the loading the .A, .X, or .Y register before actually performing the store operations. While the above example uses STA, it could have just as easily used any other store opcode.

[ Up ] [ General ] [ Specifications ] [ Compatibility ] [ GEOS ] [ Programming ] [ Timing ] [ Version 2 ]